? semiconductor components industries, llc, 2013 may, 2013 ? rev. 2 1 publication order number: NVTFS5124PL/d NVTFS5124PL power mosfet ? 60 v, ? 6 a, 260 m , single p ? channel features ? small footprint (3.3 x 3.3 mm) for compact design ? low r ds(on) to minimize conduction losses ? low q g and capacitance to minimize driver losses ? NVTFS5124PLwf ? wettable flanks product ? aec ? q101 qualified and ppap capable ? these devices are pb ? free and are rohs compliant maximum ratings (t j = 25 c unless otherwise noted) parameter symbol value unit drain ? to ? source voltage v dss ? 60 v gate ? to ? source voltage v gs 20 v continuous drain cur- rent r j ? mb (notes 1, 2, 3, 4) steady state t mb = 25 c i d ? 6.0 a t mb = 100 c ? 4.0 power dissipation r j ? mb (notes 1, 2, 3) t mb = 25 c p d 18 w t mb = 100 c 9.0 continuous drain cur- rent r ja (notes 1, 3, 4) steady state t a = 25 c i d ? 2.4 a t a = 100 c ? 1.7 power dissipation r ja (notes 1, 3) t a = 25 c p d 3.0 w t a = 100 c 1.5 pulsed drain current t a = 25 c, t p = 10 s i dm ? 24 a operating junction and storage temperature t j , t stg ? 55 to +175 c source current (body diode) i s ? 18 a single pulse drain ? to ? source avalanche energy (t j = 25 c, v dd = ? 50 v, v gs = ? 10 v, i l(pk) = ? 13 a, l = 0.1 mh, r g = 25 ) e as 8.5 mj lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. thermal resistance maximum ratings (note 1) parameter symbol value unit junction ? to ? mounting board (top) ? steady state (note 2 and 3) r j ? mb 8.4 c/w junction ? to ? ambient ? steady state (note 3) r ja 49.2 1. the entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. psi ( ) is used as required per jesd51 ? 12 for packages in which substantially less than 100% of the heat flows to single case surface. 3. surface ? mounted on fr4 board using a 650 mm 2 , 2 oz. cu pad. 4. continuous dc current rating. maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. http://onsemi.com v (br)dss r ds(on) max i d max ? 60 v 260 m @ ? 10 v ? 6 a p ? channel mosfet d (5 ? 8) s (1,2,3) g (4) wdfn8 ( 8fl) case 511ab marking diagram 380 m @ ? 4.5 v (note: microdot may be in either location) 1 xxxx = specific device code a = assembly location y = year ww = work week = pb ? free package 1 xxxx ayww d d d d s s s g see detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. ordering information
NVTFS5124PL http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) parameter symbol test condition min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = ? 250 a ? 60 v zero gate voltage drain current i dss v gs = 0 v, v ds = ? 60 v t j = 25 c ? 1.0 a t j = 125 c ? 10 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 5) gate threshold voltage v gs(th) v gs = v ds , i d = ? 250 a ? 1.5 ? 2.5 v drain ? to ? source on resistance r ds(on) v gs = ? 10 v, i d = ? 3 a 200 260 m v gs = ? 4.5 v, i d = ? 3 a 290 380 forward transconductance g fs v ds = ? 15 v, i d = ? 5 a 4 s charges and capacitances input capacitance c iss v gs = 0 v, f = 1.0 mhz, v ds = ? 25 v 250 pf output capacitance c oss 27 reverse transfer capacitance c rss 17 total gate charge q g(tot) v gs = ? 4.5 v, v ds = ? 48 v, i d = ? 3 a 3.5 nc threshold gate charge q g(th) 0.4 gate ? to ? source charge q gs 1.2 gate ? to ? drain charge q gd 1.9 total gate charge q g(tot) v gs = ? 10 v, v ds = ? 48 v, i d = ? 3 a 6 switching characteristics (note 6) turn ? on delay time t d(on) v gs = ? 4.5 v, v ds = ? 48 v, i d = ? 3 a, r g = 2.5 7 ns rise time t r 14 turn ? off delay time t d(off) 13 fall time t f 10 drain ? source diode characteristics forward diode voltage v sd v gs = 0 v, i s = ? 3 a t j = 25 c ? 0.87 ? 1.0 v t j = 125 c ? 0.74 reverse recovery time t rr v gs = 0 v, di s /dt = 100 a/ s, i s = ? 3 a 17 ns charge time t a 14 discharge time t b 3 reverse recovery charge q rr 19 nc 5. pulse test: pulse width 300 s, duty cycle 2%. 6. switching characteristics are independent of operating junction temperatures.
NVTFS5124PL http://onsemi.com 3 typical characteristics 0 2 4 6 8 012345 figure 1. on ? region characteristics ? v ds , drain ? to ? source voltage (v) ? i d , drain current (a) ? 10 v t j = 25 c v gs = ? 3 v ? 4.5 v ? 4.0 v ? 3.5 v 0 2 4 6 8 123456 v ds ? 10 v t j = 25 c t j = ? 55 c t j = 125 c figure 2. transfer characteristics ? v gs , gate ? to ? source voltage (v) ? i d , drain current (a) 0.10 0.20 0.30 0.40 0.50 246810 figure 3. on ? resistance vs. gate ? to ? source voltage ? v gs , gate ? to ? source voltage (v) r ds(on) , drain ? to ? source resistance ( ) i d = ? 3 a t j = 25 c 0.10 0.20 0.30 0.40 0.50 2 4 6 8 10 12 14 figure 4. on ? resistance vs. drain current and gate voltage ? i d , drain current (a) r ds(on) , drain ? to ? source resistance ( ) v gs = ? 4.5 v v gs = ? 10 v 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 ? 50 ? 25 0 25 50 75 100 125 150 175 figure 5. on ? resistance variation with temperature t j , junction temperature ( c) r ds(on) , drain ? to ? source resistance (normalized) v gs = ? 10 v i d = ? 3 a 10 100 1000 10000 10 20 30 40 50 60 figure 6. drain ? to ? source leakage current vs. voltage ? v ds , drain ? to ? source voltage (v) ? i dss , leakage (na) t j = 125 c t j = 150 c v gs = 0 v t j = 25 c
NVTFS5124PL http://onsemi.com 4 typical characteristics 0 100 200 300 0 102030405060 figure 7. capacitance variation ? v ds , drain ? to ? source voltage (v) c, capacitance (pf) t j = 25 c v gs = 0 v c iss c oss c rss 0 2 4 6 8 10 0246 figure 8. gate ? to ? source voltage vs. total charge q g , total gate charge (nc) ? v gs , gate ? to ? source voltage (v) v ds = ? 48 v i d = ? 3 a t j = 25 c q t q gs q gd 1.0 10.0 100.0 1000.0 1 10 100 figure 9. resistive switching time variation vs. gate resistance r g , gate resistance ( ) t, time (ns) t d(off) t d(on) t f t r v dd = ? 48 v i d = ? 3 a v gs = ? 10 v 0 10 20 30 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 ? v sd , source ? to ? drain voltage (v) ? i s , source current (a) t j = 25 c v gs = 0 v 0.1 1 10 100 1000 0.1 1 10 100 v gs = ? 10 v single pulse t c = 25 c r ds(on) limit thermal limit package limit 100 s 10 s 1 ms dc 10 ms figure 10. maximum rated forward biased safe operating area ? v ds , drain ? to ? source voltage (v) ? i d , drain current (a) figure 11. diode forward voltage vs. current 0 2 4 6 8 10 25 50 75 100 125 150 175 figure 12. maximum avalanche energy vs. starting junction temperature t j , starting junction temperature ( c) e as , single pulse drain ? to ? source avalanche energy (mj) i d = ? 13 a
NVTFS5124PL http://onsemi.com 5 typical characteristics 0.1 1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 figure 13. thermal response pulse time (sec) r ja(t) ( c/w) 0.1 duty cycle = 0.5 0.2 0.05 0.02 0.01 single pulse device ordering information device marking package shipping ? NVTFS5124PLtag 5124 wdfn8 (pb ? free) 1500 / tape & reel NVTFS5124PLwftag 24lw wdfn8 (pb ? free) 1500 / tape & reel NVTFS5124PLtwg 5124 wdfn8 (pb ? free) 5000 / tape & reel NVTFS5124PLwftwg 24lw wdfn8 (pb ? free) 5000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NVTFS5124PL http://onsemi.com 6 package dimensions wdfn8 3.3x3.3, 0.65p case 511ab issue d m 1.40 1.50 0 ??? 1.60 12 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension d1 and e1 do not include mold flash protrusions or gate burrs. 1234 5 6 top view side view bottom view d1 e1 d e b a 0.20 c 0.20 c 2x 2x dim min nom millimeters a 0.70 0.75 a1 0.00 ??? b 0.23 0.30 c 0.15 0.20 d d1 2.95 3.05 d2 1.98 2.11 e e1 2.95 3.05 e2 1.47 1.60 e 0.65 bsc g 0.30 0.41 k 0.65 0.80 l 0.30 0.43 l1 0.06 0.13 a 0.10 c 0.10 c detail a 14 8 l1 e/2 8x d2 g e2 k b a 0.10 b c 0.05 c l detail a a1 e 6x c 4x c seating plane 5 max 0.80 0.05 0.40 0.25 3.15 2.24 3.15 1.73 0.51 0.95 0.56 0.20 m *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.65 0.42 0.75 2.30 3.46 package 8x 0.055 0.059 0 ??? 0.063 12 0.028 0.030 0.000 ??? 0.009 0.012 0.006 0.008 0.116 0.120 0.078 0.083 0.116 0.120 0.058 0.063 0.026 bsc 0.012 0.016 0.026 0.032 0.012 0.017 0.002 0.005 0.031 0.002 0.016 0.010 0.124 0.088 0.124 0.068 0.020 0.037 0.022 0.008 min nom inches max 7 8 pitch 3.60 0.57 0.47 outline dimension: millimeters 3.30 bsc 3.30 bsc 0.130 bsc 0.130 bsc 2.37 0.66 4x e3 0.23 0.30 0.40 0.009 0.012 0.016 e3 4x on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NVTFS5124PL/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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